In fabricating highly-integrated memory devices, a capacitor has to provide a relatively high capacitance in a small area. Conventionally, capacitance can be increased by forming a capacitor using a dielectric layer with a large dielectric constant, forming a thin dielectric layer, and/or increasing a cross-sectional area of a capacitor.
Known multi-layered capacitors or trench-type capacitors have been used to increase a cross-sectional area of a capacitor. A half-spherical polysilicon layer has also been used to that end. However, these known technologies tend to complicate a capacitor structure, reduce process yield, and increase manufacturing cost.
Dielectric materials including SiO2/Si3N4 are used as commonly used as a dielectric layer of a capacitor. Based on the material used for a capacitor electrode, a polysilicon-insulator-polysilicon (PIP) capacitor structure or a metal-insulator-metal (MIM) capacitor structure may be employed. Thin film capacitors such as PIP capacitors and MIM capacitors are used in analog semiconductor devices requiring precise capacitance values because, in contrast to MOS capacitors and junction capacitors, these capacitors are independent of bias.
In addition, although the MIM capacitor has a disadvantage because it has smaller capacitance per unit area than that of the PIP capacitor, the former has better VCC (voltage coefficient for capacitance) and TCC (temperature coefficient for capacitance) according to voltage and temperature as compared to the PIP capacitor.
FIGS. 1a through 1f illustrate, in cross-sectional views, the process steps of a known capacitor-fabricating method. Referring to FIG. 1a, a dielectric layer 3 is deposited on a lower metal layer 2 and a substrate 1 with at least a predetermined structure, and an upper metal layer 4 is deposited on the dielectric layer. Referring to FIG. 1b, a MIM capacitor 5 is formed by etching simultaneously the dielectric layer and the upper metal layer using a mask (not shown). Referring to FIG. 1c, an interlayer dielectric 6 is formed on all of the area of the substrate with the MIM capacitor. Referring to FIG. 1d, the interlayer dielectric is etched to form a via hole that connects the upper metal layer and the lower metal layer, respectively, with an uppermost metal layer, and a barrier metal layer 7 is deposited on the via hole. Referring to FIG. 1e, the via hole is filled with a metal plug 8 and flattened to complete the contact via hole. Referring to FIG. 1f, a metal layer is deposited on the metal plug 8 and patterned to form an uppermost metal layer 9, thereby completing a MIM capacitor.
Korean Patent Publication No. 10-2003-0058317 discloses a MIM capacitor fabricating method that forms an etch stopping layer to prevent the interlayer dielectric from being attacked by etching solution and eliminating an oxide supporting a lower electrode. Another Korean Patent Publication No. 10-2002-0073822 discloses a method of fabricating a MIM capacitor that provides good step coverage and a uniform dielectric layer and forms spacers on lateral walls of a lower electrode.
However, in these conventional methods the process of forming an MIM capacitor by etching simultaneously an upper metal layer and a dielectric layer, causes a fringing effect at the edge of the MIM capacitor, and is accompanied by bridge, which increases leakage current. The bridge is generated by redeposition of metal etched from the lower metal layer during over-etching necessary for etching a dielectric layer of MIM capacitor. To obviate these problems, the formation of spacers on a lower electrode has been proposed, but such spacers do not completely prevent the bridge due to the difficulty in controlling the process and, in some cases, may significantly complicate processing.